搜索结果: 1-15 共查到“Intel”相关记录36条 . 查询时间(0.203 秒)
当地时间2月21日，Intel Foundry Direct Connect 2024在美国圣何塞举办。大会期间，Intel宣布推出为AI时代打造的系统级代工——Intel Foundry，并公布了2024年以后的7个全新工艺节点，其中包括采用High-NA EUV设备的下一代Intel 14A和14A-E工艺。
We show how to build a practical, private data oblivious genome variants search using Intel SGX. More precisely, we consider the problem posed in Track 2 of the iDash Privacy and Security Workshop 201...
We are witnessing a confluence between applied cryptography and secure hardware systems in enabling secure cloud computing. On one hand, work in applied cryptography has enabled efficient, oblivious d...
西安电子科技大学计算机学院微机系统及应用（一）课件第三章 Intel处理器指令系统及汇编语言（3）
西安电子科技大学计算机学院 微机系统及应用 课件 第三章 Intel处理器指令系统及汇编语言
2016/2/24
西安电子科技大学计算机学院微机系统及应用（一）课件第三章 Intel处理器指令系统及汇编语言（3）。
西安电子科技大学计算机学院微机系统及应用（一）课件第三章 Intel处理器指令系统及汇编语言（2）
西安电子科技大学计算机学院 微机系统及应用 课件 第三章 Intel处理器指令系统及汇编语言
2016/2/24
西安电子科技大学计算机学院微机系统及应用（一）课件第三章 Intel处理器指令系统及汇编语言（2）。
西安电子科技大学计算机学院微机系统及应用（一）课件第三章 Intel处理器指令系统及汇编语言（1）
西安电子科技大学计算机学院 微机系统及应用 课件 第三章 Intel处理器指令系统及汇编语言
2016/2/24
西安电子科技大学计算机学院微机系统及应用（一）课件第三章 Intel处理器指令系统及汇编语言（1）。
Intel SGX Explained
SGX hypervisor
2016/2/23
Intel's Software Guard Extensions (SGX) is a set of extensions to the Intel architecture that aims to provide integrity and privacy guarantees to security-sensitive computation performed on a computer...
A Provable Security Analysis of Intel's Secure Key RNG
random number generator entropy extraction provable security
2016/1/8
We provide the first provable-security analysis of the Intel Secure Key hardware RNG
(ISK-RNG), versions of which have appeared in Intel processors since late 2011. To model the ISKRNG,
we generaliz...
Who watches the watchmen? : Utilizing Performance Monitors for Compromising keys of RSA on Intel Platforms
Branch misprediction HPC public-key cipher, side-channel
2015/12/29
Asymmetric-key cryptographic algorithms when implemented on systems with branch predictors, are subjected to side-channel attacks exploiting the deterministic branch predictor behavior due to their ke...
Systematic Reverse Engineering of Cache Slice Selection in Intel Processors
Cache slices Intel last level cache,
2015/12/29
Dividing last level caches into slices is a popular method to prevent memory accesses from
becoming a bottleneck on modern multicore processors. In order to assess and understand the benefits
of cac...
Modern Intel processors use an undisclosed hash function to map memory lines into last-level cache
slices. In this work we develop a technique for reverse-engineering the hash function. We apply the ...
A Fast Implementation of the Optimal Ate Pairing over BN curve on Intel Haswell Processor
optimal ate pairing efficient implementation
2014/3/12
We present an efficient implementation of the Optimal Ate Pairing on Barreto-Naehrig curve over a 254-bit prime field on Intel Haswell processor. Our library is able to compute the optimal ate pairing...
Impact of Intel's New Instruction Sets on Software Implementation of $GF(2)[x]$ Multiplication
implementation / $GF(2)[x]$ multiplication Karatsuba Algorithm SSE AVX PCLMULQDQ
2012/3/22
PCLMULQDQ, a new instruction that supports $GF(2)[x]$ multiplication, was introduced by Intel in 2010. This instruction brings dramatic change to software implementation of multiplication in $GF(2^m)$...
Impact of Intel's New Instruction Sets on Software Implementation of $GF(2)[x]$ Multiplication
implementation / $GF(2)[x]$ multiplication Karatsuba Algorithm SSE AVX PCLMULQDQ
2012/3/21
PCLMULQDQ, a new instruction that supports $GF(2)[x]$ multiplication, was introduced by Intel in 2010. This instruction brings dramatic change to software implementation of multiplication in $GF(2^m)$...
